Single Device Characterization

by Nano-Probing in a SEM


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3 Manipulators


The following text is an extract from a paper published by TSMC, Taiwan:

In general failure analysis cases, a less invasive fault isolation approach can be utilized to resolve a visual root cause defect. In the case of nano technology, visual defects are not readily resolved, due to an increase in non-visible defects. The non-visible defects result in a lower success rate since conventional FA methods/tools are not efficient in identifying the failure root cause. For the advanced nanometer process, this phenomenon is becoming more common; therefore the utilization of advanced techniques are required to get more evidence to resolve the failure mechanism. The use of nanoprobe technology enables advanced device characterization in order to obtain more clues to the possible failure mechanism before utilizing the traditional physical failure analysis techniques:

A wafer probing system with three micromanipulators (Klocke Nanotechnik) installed in a Hitachi FE-SEM S-4800.

Nano-probing is capable of directly measuring the behavior of source/drain junctions with a single probe, resistance measurement of two contacts with two probes and full transistor characterization with multiple probes. Basic transistor parameters such as Vt, Ioff, Isat, and junction behavior can be identified by means of I/V curves measurements. This capability will help guide the root cause failure analysis when comparing the measured data with reference data.

A wafer probing system with three micromanipulators (Klocke Nanotechnik) was used in the measurements, which was installed into a Hitachi FE-SEM S-4800. Utilizing this nano-probing technique, we can measure the device characteristics at the contact level:

Device behavior is different between the PMOS transistors of bad and good dice. The device of bad die has higher Ioff.

After comparing the I/V curves of the emitting PMOS transistor with a reference PMOS transistor, an abnormal electrical characteristic can be observed on the emitting transistor (See Figure above). The I/V curve of bad transistor shows a lower Isat and higher Ioff current. In order to understand the leakage path, the current components of Source, Drain, Gate, and Well/substrate node shall be checked (See followingTable). Analysis of the electrical results indicates the leakage path of the emitting transistor is between drain and substrate.

The table shows the current value of source, drain, gate and well/substrate. Strong signals labeled with red indicate leakage existed between drain and substrate.


Generally, nano-probing system is a powerful tool for electrical analysis; it can be used to characterize junction
behavior, short/resistance and transistor/diode measurements. For device behavior checking, the basic parameters, such as Vt, Ioff, and Isat can be measured easily, and the current flow to source, drain, gate, and well/substrate should also be identified to realize the leakage path.
Because WAT parameters can’t accurately reflect real device behavior in circuit, the nano-probing measurements on suspected transistors are needed. It can obtain more electrical data to provide more hints and saving more time to identify the root cause for the FA of 130nm technology and below.

This application paper from TSMC describes, how effective Wafer Probing Systems from Klocke Nanotechnik are for device characterization.
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